Table of Contents
Advertisement
µ PD78214 Sub-Series
#
130
Fig. 7-25 Setting of Control Registers for Interval Timer Operation (1)
(a) Timer control register 0 (TMC0)
7
6
×
0
TMC0
(b) Capture/compare control register 0 (CRC0)
7
6
5
CRC0
0
0
0
Fig. 7-26 Setting Procedure for Interval Timer Operation (1)
Set count value in CR00 register
5
4
3
2
0
0
0
1
4
3
2
1
0
0
Interval
timer (1)
CR00←n
Set CRC0 register
CRC0←10H
Start counting
CR0←1
INTC00 interrupt
1
0
0
0
Overflow flag
Enables counting TM0
1
0
0
0
Disables clearing TM0
Both TO0 and TO1 are used for
toggle output
; Sets bit 3 of TMC0 to 1
Advertisement
Table of Contents
