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µ PD78214 Sub-Series
2. If the current value of the CR01 compare register is decreased below the value of 16-bit timer 0 (TM0), the PPG period becomes
as long as the full-count time of TM0. At this time, if CR01 is rewritten after the value of the CR00 compare register coincides
with the value of TM0, the inactive level is output until TM0 overflows to 0, then normal PPG output is resumed. If CR01 is
rewritten before the value of CR00 coincides with the value of TM0, the active level is output until the value of CR00 coincides
with the value of TM0. When the value of CR00 coincides with the value of TM0 before TM0 overflows to 0, the inactive level
is output at that time. When TM0 overflows to 0, the active level is output, and normal PPG output is resumed. Rewrite CR01,
if required, by using an interrupt generated by a coincidence between TM0 and CR01.
n1
TM0
0H
CR00
CR01
TO0
Remark ALV0 = 1
3. If the PPG period is too short for interrupt acceptance, the measures described in Cautions 1 and 2 above do not lead to solution.
Consider other measures (such as masking all interrupts and polling interrupt request flags by software).
4. If timer output is disabled (ENTOn = 0: n = 0, 1), the output level on the TOn (n = 0, 1) pin is the inverted value of the value set
in ALVn (n = 0, 1). Accordingly, note that if timer output is disabled when the PPG output function is selected, the active level
is output.
128
Fig. 7-23 Example of PPG Output Period Made Longer
n1
n3
n3
n1
The PPG period is extended when a value,
n2 less than TM0 value, n5 is written to
CR01 here.
Full count value
n1
n3
n5
n2
TO0 becomes inactive when CR00 coincides with TM0;
otherwise, TO0 remains active.
n2
n4
n4
n2
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