Interrupt Status Register (Ist); Interrupt Status Register (Ist) Format - NEC PD78212 User Manual

When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higher
priorities are accepted for multiple-interrupt handling provided that interrupts are enabled. When a high-priority
interrupt is being handled, high-priority vectored interrupts are accepted for multiple-interrupt handling provided
that interrupts are enabled. Moreover, any interrupt requests specifying a macro service are accepted regardless
of their priority.
When the RESET signal is input, this register is set to FFFFH, thereby specifying that all interrupts be in the low-
priority group.
7
PR0L CPR11 CPR10 CPR01 CPR00 PPR3
PR0H CSIPR STPR

12.2.5 Interrupt Status Register (IST)

The IST register is an 8-bit register that controls multiple-interrupt handling for nonmaskable interrupt requests
(input to the NMI pin) and indicates whether a nonmaskable interrupt request has been accepted.
When a nonmaskable interrupt is being handled, another nonmaskable interrupt request may occur. In such a
case, the nonmaskable interrupt request is accepted if the NMIS bit is 0; it is not accepted if the NMIS bit is 1.
The NMIS bit is set to 1 when a nonmaskable interrupt request is accepted. It is reset to 0, when a return (execution
of the RETI instruction) from the interrupt handling for the nonmaskable interrupt request occurs.
Both an 8-bit manipulation instruction and bit manipulation instruction can be used to read data from and write
data to the IST register. The NMIS flag is set to 1 when a nonmaskable interrupt is accepted. It is reset to 0 by the
RETI instruction. Fig. 12-7 shows the format of the IST register.
When the RESET signal is input, the register is reset to 00H.
7 6
IST 0 0
Fig. 12-6 Priority Specification Flag Register (PR0) Format
6 5 4 3
PPR2
SRPR SERPR CPR20 PPR5
Fig. 12-7 Interrupt Status Register (IST) Format
5 4 3 2 1
0 0 0 0 0
Multiple interrupt processing by
NMIS
nonmaskable interrupt request
0 Enabled
1 Disabled
Chapter 12 Interrupt Functions
2 1 0
PPR1 PPR0 (FFFFH when RESET signal is input)
PPR4 CPR21
Priority specification flags
0 High priority
1 Low priority
0
NMIS
Accepting status for
nonmaskable interrupt request
Execution exits from nonmaskable
interrupt processing or nonmaskable
interrupt request is not accepted.
Nonmaskable interrupt request is
accepted or being processed.
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