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7
6
PM5
PM57
PM56
For the µ PD78213, port 4 functions only as the address/data bus (AD8 through AD15).
5.6.3 Operation
Port 5 is an I/O port. Its pins also function as control signal pins.
(1) Output port
When port 5 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can
be transferred between the output latch and the accumulator using a transfer instruction. The output latch can
be loaded with any data by a logical operation instruction. Once the output latch is loaded with some data, it retains
the data until it is loaded
Note This includes a case in which any other bit of the same port is manipulated using a bit manipulation instruction.
(2) Input port
The level of each pin of port 5 can be transferred to the accumulator by a transfer instruction. Also in this case,
data can be written to the output latches, and all output latches store data transferred from the accumulator
by a transfer instruction or other similar instruction, regardless of the current mode of the port operation. If
a bit is specified as an input port, however, the latched data is not output to the port pin because the output
buffer at the pin is in the high-impedance state. (When the pin is switched from the input mode to the output
mode, the contents of the output latch are output to the port pin.) If a bit is specified as an input port, the
contents of the output latch for the pin cannot be transferred to the accumulator.
Fig. 5-28 Port 5 Mode Register Format
5
4
3
2
PM55
PM54
PM53
PM52
Table 5-6 Port 5 Operating Modes
MM register bit
EA pin
MM2
MM1
1
0
0
1
1
1
×
×
0
Note
with other data.
Fig. 5-29 Port Specified as an Output Port
WR
PORT
Output
Iatch
RD
OUT
1
0
(FFH when RESET is input)
PM51
PM50
PM5n
Specifies I/O mode of pin PM5n (n = 0 to 7)
0
Output mode (output buffer ON)
1
Input mode (output buffer OFF)
Operation mode
MM0
×
I/O port
1
Address/data bus
(A8-A15)
×
P5n
n = 0 to 7
Chapter 5 Port Functions
5
81
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