Configuration Of General-Purpose Registers - NEC PD78212 User Manual

µ PD78214 Sub-Series
0FEE0H
0FEFFH
To specify the register bank to be used to execute an instruction, use the CPU control instruction (SEL RBn).
When RESET is input, register bank 0 is specified.
The current register bank can be checked by reading the register bank selection flags (RBS0, RBS1) in the PSW.
The area from 0FEE0H to 0FEFFH can be addressed and accessed as an ordinary data memory area,
irrespective of whether the area is used for general-purpose registers.
Remark To restore the current register bank after it is changed to a different register bank, execute the PUSH PSW instruction to save the PSW
to a stack, then execute the SEL RBn instruction. The POP PSW instruction can restore the register bank if the stack position is not
changed. If an interrupt handling program changes the register bank, the PSW is automatically saved to a stack when an interrupt
is acknowledged. The PSW is restored by the RETI or RETB instruction. If a single register bank is predetermined for the interrupt
handling routine, only the SEL RBn instruction need be executed. The PUSH PSW instruction need not be executed.
Examples 1. Changing the register bank by an ordinary program
Specifying register bank 2
PUSH PSW
SEL
POP
2. Changing the register bank by an interrupt handling program
Selecting register bank 1
SEL
RETI
48
Fig. 3-11 Configuration of General-Purpose Registers
(8-bit processing)
A X
E1H E0H
B C
E3H E2H
D E
E5H E4H
H L
E7H E6H
A X
E9H E8H
B C
EBH EAH
D E
EDH ECH
H L
EFH EEH
A X
F1H F0H
B C
F3H F2H
D E
F5H F4H
H L
F7H F6H
A X
F9H F8H
B C
FBH FAH
D E
FDH FCH
H L
FFH FEH
· ·
· ·
·
RB2
· ·
· ·
Register bank 2 is used.
·
PSW
· ·
· ·
The previous register bank is used.
·
RB1
Register bank 1 is used.
· ·
The previous register bank is automatically
· ·
·
restored upon return from the interrupt
handling program.
(16-bit processing)
↑
Register bank 3
(RBS1, 0 = 11)
↓
↑
Register bank 2
(RBS1, 0 = 10)
↓
↑
Register bank 1
(RBS1, 0 = 01)
↓
↑
Register bank 0
(RBS1, 0 = 00)
↓
AX
E0H
BC
E2H
DE
E4H
HL
E6H
AX
E8H
BC
EAH
DE
ECH
HL
EEH
AX
F0H
BC
F2H
DE
F4H
HL
F6H
AX
F8H
BC
FAH
DE
FCH
HL
FEH