Example Of Setting The Brgc Register When The Baud Rate Generator For Uart Is Used; Baud Rate Setting - NEC PD78212 User Manual

µ PD78214 Sub-Series

9.5 BAUD RATE SETTING

The baud rate can be set by three methods listed in Table 9-2.
The table indicates the ranges of baud rates that can be generated by each method, the baud rate calculation
formulas, and the selection methods.
Baud rate clock source
Baud rate Internal
generator system clock
for UART
ASCK input
8-bit timer/counter 3
f : Internal system clock frequency
CLK
k : Value set in the MDL3 through MDL0 bits of the BRGC register (k = 1 through 14; see Fig. 9-9.)
1/n : Frequency divider tap (n = 2, 4, 8, 16, 32, 64, 128, 256)
f : Frequency of the ASCK input clock (0 – f
ASCK
1/16 : Serial data sampling rate
j : Value set in the PRS3 through PRS0 bits of prescaler mode register 0 (j = 0 through 6)
m : Value set in the 8-bit compare register (CR30); m = 0 through 255
Note 0 – f /384 if the f
CLK ASCK

9.5.1 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used

This section shows examples of setting the BRGC register when the baud rate generator for UART is used.
To use the baud rate generator, set the SCK bit of the asynchronous serial interface mode register (ASIM) to 1.
254
Table 9-2 Baud Rate Setting
Selection method
SCK of the ASIM MDL0 through MDL3 of the
register = 1 BRGC register = 0H to EH
CE of the BRGC
MDL0 through MDL3 of
register = 1
the BRGC register = FH
SCK of the ASIM register = 0
CLK
PRS3-PRS0 0H
j 0
input range is included.
Calculation formula
f
K + 1
f
ASCK
f
2
m + 1
/24)
1H 2H 3H 4H 5H
1 2 3 4
Baud rate range
1 1 f
CLK CLK
× ×
–
n 16 61440
2 1 f
ASCK
× ×
–
n 16 2048
CLK
f
CLK
j + 3
1 1
× ×
4194304
16 2
6H 7H
5 6
f
CLK
64
Note
f
ASCK
16
f
CLK
–
256