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µ PD78214 Sub-Series
(1) Selecting the internal clock as the serial clock
When transmission and reception are started, the serial clock is output from the SCK pin. In synchronization
with the falling edge of the serial clock, data is sequentially output from the SIO to the SO pin. In
synchronization with the rising edge of the serial clock, data is sequentially shifted in from the SI pin to the
SIO.
It takes up to one cycle of the SCK clock to drive SCK low for the first time, after the transmission and reception
are started.
If either transmission or reception is inhibited during transmission and reception, only the inhibited operation
is halted. If transmission is inhibited, the output from the SO pin goes to the high-impedance state. If reception
is inhibited, the contents of the SIO register become undefined.
If transmission and reception are simultaneously inhibited, the output of the SCK clock is stopped and
transmission and reception are halted at the next rising edge of SCK. If this occurs, the contents of the SIO
become undefined. No interrupt request (INTCSI) is issued. The output from the SO pin goes to the high-
impedance state.
(2) Selecting an external clock as the serial clock
When transmission and reception are started, data is sequentially output from the SIO to the SO pin in
synchronization with the falling edge of the serial clock input to the SCK pin, after the start of the transmission
and reception. In synchronization with the rising edge of the serial clock, data is sequentially shifted in from
the SI pin to the SIO. If the serial clock is input to the SCK pin before transmission and reception have been
started, shift into the SIO does not occur. The output level of the SO pin does not change.
If either transmission or reception is inhibited during transmission and reception, only the inhibited operation
is halted. If transmission is inhibited, the output from the SO pin goes to the high-impedance state. If reception
is inhibited, the contents of the SIO become undefined.
If transmission and reception are simultaneously inhibited, transmission and reception are halted and the
subsequent SCK input is ignored. If this occurs, the contents of the SIO become undefined. No interrupt
request (INTCSI) is issued. The output from the SO pin goes to the high-impedance state.
10.4.5 Action to Be Taken When the Serial Clock and Shift Become Asynchronous
If the external clock is selected as the serial clock, the serial clock and shift may become asynchronous because
of noise. If this occurs, inhibit both transmission and reception (reset the CTXE and CRXE bits to 0). This initializes
the serial clock counter. Then, the shift and serial clock are synchronized again at the first serial clock pulse input,
after either transmission or reception is permitted.
10.5 SBI MODE
SBI (serial bus interface) is a high-speed serial interface conforming to the NEC serial bus format.
SBI is a high-speed serial bus with a single master, consisting of a clock synchronous serial I/O and a bus
configuration function. In SBI mode, the device can communicate with two or more devices over two signal lines.
If the serial bus is configured with two or more microcomputers and peripheral ICs, the number of ports and lines
on the board can be reduced.
For details of the SBI functions, refer also to "Serial Bus Interface (SBI) User's Manual (IEM-1303)".
10.5.1 Features of SBI
Conventional serial I/O supports only data transfer. If the serial bus is configured with two or more devices, many
ports and lines are required for the chip select signal, the separation of commands from data, and judgment of
the busy state. If they are controlled by the software, an excessive load will be applied to the software.
If SBI is used, two signal lines, serial clock SCK and serial data bus line SB0, can form the serial bus. The number
of ports for the microcomputers and lines on the printed circuit board can thus be reduced.
The SBI functions are described below:
(1) Function to separate address, command, and data
This function separates serial data into an address, command, and data.
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