Pwm Pulse Output; Pwm Output On To0 And To1 - NEC PD78212 User Manual

µ PD78214 Sub-Series
7.1.7 PWM Output
The PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer
0 (TM0). The pulse width of TO0 is determined by the value of CR00, and the pulse width of TO1 is determined
by the value of CR01. Before this function can be used, the CLR01 bit of capture/compare control register 0 (CRC0)
must be set to 0.
The pulse period and pulse width are as follows:
• PWM period = 524288/f
• PWM pulse width = (value set in compare register
Note Zero cannot be set in the compare registers.
• Duty factor = (PWM pulse width)/(PWM period) = ((value set in compare register) × 8 + 2)/(65536 × 8)
set in compare register)/65536
Caution In PWM output, the actual pulse width is longer than a value obtained with the approximate expression by two clock pulses of f
for the active level, and is shorter than such an approximate value by two clock pulses of f
into consideration when high-precision output is required.
Count value of timer
Interrupt
Count clock
Fig. 7-14 shows an example of 2-channel PWM output. Fig. 7-15 shows PWM output when FFFFH is set in the CR00
compare register.
122
CLK
Fig. 7-13 PWM Pulse Output
CR00
Count starts
0H
TO0
Remark ALV0 = 0
Table 7-7 PWM Output on TO0 and TO1 (f
Minimum pulse width
1.3 µ s
f /8
CLK
) × 8 + 2/f (value set in compare register) × 8/f
Note
CLK
FFFFH FFFFH
CR00
Pulse width
Pulse period
= 6 MHz)
CLK
PWM period
87.4 ms
for the inactive level. Take this point
CLK
FFFFH
CR00
Pulse width
Pulse period
PWM frequency
11.4 Hz
CLK
(value
CLK