Table of Contents
Advertisement
11.3 EDGE DETECTION ON PINS P21 TO P26
An edge on pins P21 to P26 is detected after digital noise elimination by means of clock sampling.
The digital noise elimination is performed by means of sampling with the f
eliminated as noise if an identical level is not obtained three or more times in a row (even if an identical level is
consecutively obtained twice). The input signal is detected as a valid edge only when its level remains identical
for three or more cycles of the f
P21 to P26
f
/4
CLK
P21 to P26
after noise rejection
Rising edge
Falling edge
Cautions 1. Because the f
CLK
after the edge is actually input.
2. If the width of an input pulse corresponds to 8 to 12 cycles of the f
detected as a valid edge. To ensure the accurate detection of a pulse, hold the pulse at an identical level for 12 clock cycles
or longer.
3. If noise input to a pin is synchronized with the f
such noise is possible, add a filter to the input pin to eliminate the noise.
4. An in-circuit emulator cannot successfully eliminate digital noise. It may erroneously detect a falling edge due to noise during
the input of a low signal and a rising edge due to noise during the input of a high signal (see Fig. 11-5). When data is read from
port 2, noise is not eliminated, being read instead.
INTPn input (n = 0 to 6)
After noise rejection
Falling edge detection
Rising edge detection
/4 clock (2 µ s: f
CLK
Fig. 11-4 Edge Detection on Pins P21 to P26
Digital noise is rejected at f
/4 clock is used for digital noise elimination, it takes about 8 to 12 cycles of the f
Fig. 11-5 Erroneously Detected Edges
(a) Erroneously detected edge during input of a low signal
f
/4
CLK
Chapter 11 Edge Detection Function
= 6 MHz).
CLK
/4 clock.
CLK
clock, it cannot be determined whether the pulse is
CLK
/4 clock of the µ PD78214, it may not be judged as being noise. If input of
CLK
Noise
"L"
Erroneously detected edge
/4 clock. The input signal is
CLK
clock to detect an edge
CLK
11
297
Advertisement
Table of Contents
