Transmission; Asynchronous Serial Interface Transmission Completion Interrupt Timing - NEC PD78212 User Manual

µ PD78214 Sub-Series
• Odd parity
In contrast to even parity, the parity bit for odd parity is controlled so that the number of 1 bits in the transmit
data becomes odd. When data is received, the number of 1 bits in it is counted, and if the number of 1 bits is
even, a parity error is detected.
• 0 parity
When data is transmitted, the parity bit is reset to 0, regardless of what the transmit data is like. During reception,
the parity bit is not checked. Therefore, a parity error is not detected, regardless of whether the parity bit is 0
or 1.
• No parity
No parity bit is attached to the transmit data. The reception end assumes that there is no parity bit. Because
no parity bit is used, no parity error is detected.

9.3.3 Transmission

The asynchronous serial interface for the µ PD78214 is always ready to transmit data. Writing transmit data to the
transmission shift register (TXS) triggers transmission. The start bit, parity bit, and stop bit(s) are attached
automatically.
When transmission is triggered, the transmission shift register (TXS) shifts out its contents. When the register
becomes empty, a transmission completion interrupt (INTST) occurs.
If no further transmission data is written to the transmission shift register (TXS), transmission breaks.
Fig. 9-5 Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
TxD (Output)
INTST
(b) Stop bit length: 2
TxD (Output)
INTST
Cautions 1. When the RESET signal is input, the transmission shift register becomes empty, but no transmission completion interrupt
occurs. Transmission is triggered by writing the transmit data to the transmission shift register.
2. The asynchronous serial interface mode register (ASIM) must not be modified during transmission. If the ASIM register is
modified during transmission, further transmission becomes impossible (inputting the RESET signal resumes normal
operation).
Software can determine whether transmission is in progress, using the transmission completion interrupt (INTST) or the
interrupt request flag (STIF), which is set by the INTST.
248
D0 D1 D2
START
D0 D1 D2
START
STOP
D6 D7 Parity
STOP
Parity
D6 D7