Pwm Pulse Output; Pwm Output; To2 And To3 Toggle Output - NEC PD78212 User Manual

µ PD78214 Sub-Series
Caution When using an in-circuit emulator, see the notes described in Section 7.5.4.

7.3.9 PWM Output

The PWM output function outputs a PWM signal whose period coincides with the full-count period of 8-bit timer
2 (TM2). The pulse width of TO2 is determined by the value of CR20, and the pulse width of TO3 is determined
by the value of CR21. Before this function can be used, the CLR21 and CLR22 bits of capture/compare control
register 2 (CRC2) must be set to 0, and the CMD2 bit of timer control register 1 (TMC1) must be set to 0.
The pulse period and pulse width are as follows:
• PWM period = 256 × x/f
• PWM pulse width = ((value set in compare register
Note Zero cannot be set in the compare registers.
• Duty factor = (PWM pulse width)/(PWM period) = ((value set in compare register) × x + 2)/(256 × x) (value set
in compare register)/256
Caution In PWM output, the actual pulse width is longer than a value obtained with the approximate expression by two clock pulses of f
#
for the active level, and is shorter than such an approximate value by two clock pulses of f
into consideration when high-precision output is required or a high-speed count clock is used.
Count value of timer
Interrupt
182
Table 7-16 TO2 and TO3 Toggle Output (f
Count clock Minimum pulse width
f /16
CLK
f /32
CLK
f /64
CLK
f /128
CLK
f /256
CLK
f /512
CLK
CLK
; x = 16, 32, 64, 128, 256, 512
Fig. 7-85 PWM Pulse Output
CR20
Count starts
0H
TO2
Remark ALV2 = 0
CLK
Maximum pulse width
2
2.6 µ s
2
5.3 µ s
2
10.7 µ s
2
21.3 µ s
2
42.7 µ s
2
85.3 µ s
(21.75 ms)
) × x + 2)/f
Note
CLK
FFH
FFH
CR20
Pulse width
Pulse period
= 6 MHz)
× 16/f
8
CLK
(683 µ s)
× 32/f
8
CLK
(1.37 ms)
× 64/f
8
CLK
(2.73 ms)
× 128/f
8
CLK
(5.46 ms)
× 256/f
8
CLK
(10.9 ms)
× 512/f
8
CLK
for the inactive level. Take this point
CLK
FFH
CR20
Pulse width
Pulse period
CLK