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TM2 can also be cleared by software when the CE2 bit of the timer control register (TMC1) is reset to 0.
Similarly, clear operation is performed by the count clock pulse following the resetting of CE2 bit to 0. If the
CE2 bit is set to 1 before TM2 is reset to 0 by the resetting of the CE2 bit to 0 (that is, before the first count clock
pulse is applied after the CE2 bit is reset to 0), two operations are simultaneously performed: one operation
is an operation to clear TM2 to 0, and the other operation is a count operation starting with the counting of
0.
(a) Basic operation
Count clock
(b) Restart after 0 is set in TM2 cleared
Count clock
Fig. 7-74 Clear Operation When the CE2 Bit Is Reset to 0
n-1
n
TM2
CE2
n-1
n
TM2
CE2
When the CE2 bit is set to 1 aftr this count clock,
counting starts from 0 on the count clock input
after the CE2 bit has been set.
Chapter 7 Timer/Counter Units
0
1
0
0
7
169
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