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µ PD78214 Sub-Series
Signal source
The voltage input to the AN0 to AN7 pins must be maintained at a level between V
falling outside this range increases the current consumption as well as adversely affecting the reliability of
the microcomputer.
14.5 NOTES
(1) If HALT mode is specified under the conditions for releasing HALT mode, the system does not enter HALT
mode, instead executing the next instruction or branching to the vectored interrupt service program. Clear
any interrupt requests before specifying HALT mode to ensure that the system correctly enters HALT mode.
(2) In STOP mode, the X1 pin is internally short-circuited to VSS (ground potential) to prevent current leakage
from the clock oscillator circuit. STOP mode must not, therefore, be specified for a system using an external
clock.
(3) Reset the CS bit for the A/D converter before specifying STOP mode.
(4) The system enters STOP mode even if an NMI request is held when STOP mode is specified. When using an
NMI request to release STOP mode, input the NMI signal again.
#
(5) If another effective edge of the NMI signal is detected during the oscillation settling time, the oscillation
settling time counter is cleared and restarts counting, resulting in a longer wait time than usual. The extra
wait time is the total of the time from the end of the first active level to detection of the next effective edge
and the width of the second active level, starting from its effective edge. Fix the NMI signal at the inactive level
during the oscillation settling time, to ensure the correct release of STOP mode.
386
Fig. 14-8 Example Arrangement for Analog Input Pin
Power supply not backed up
Diode with
small V
F
Power supply backed up
V
DD
AV
REF
µ
PD78214
ANn (n = 0 to 7)
V
SS
and V
SS
. Any voltage
DD
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