Table of Contents
Advertisement
SCK
6
SB0
D2
ACKT
Caution Do not set ACKT before transfer has been completed.
(a) When ACKE is set to 1 at the end of transfer
SCK
SB0
ACKE
(b) When ACKE is set after transfer has been completed
SCK
6
SB0
D2
ACKE
(c) When ACKE is set to 0 at the end of transfer
SCK
SB0
ACKE
Fig. 10-23 ACKT Operation
7
8
9
D1
D0
When set during this period
Fig. 10-24 ACKE Operations
1
2
7
D7
D6
D2
D1
7
8
9
D1
D0
When ACKE is set during this period and ACKE = 1 at
the falling edge of the next SCK
1
2
7
D7
D1
D6
D2
Chapter 10 Clock Synchronous Serial Interface
ACK signal is output during first clock
cycle immediately after ACKT is set.
ACK
8
9
The ACK signal is output
D0
ACK
during the ninth clock
cycle
When ACKE = 1 at this point
The ACK signal is output
ACK
during the first clock cycle
immediately after ACKT is set.
8
9
The ACK signal is not
output
D0
When ACKE = 0 at this point
10
281
Advertisement
Table of Contents
