Table of Contents
Advertisement
µ PD78214 Sub-Series
Fig. 6-9 Interrupt Request Handling When the Real-Time Output Function Is Used
6.6 NOTES
(1) When the P0ML or P0MH is set to 1, the output buffer for the corresponding output port is turned on to output
the contents of the port 0 output latch, regardless of the contents of the port 0 mode register (PM0). Therefore,
initialize the contents of the output latch before specifying the real-time output port.
(2) When port 0 is used as a real-time output port, values cannot be written directly to the output latch by software.
Therefore, the output latch must be set with the initial value by software beforehand, if necessary.
If it is necessary to forcibly change the output data into a constant value when port 0 is used as a real-time
output port, put port 0 in an ordinary output mode by manipulating the RTPC, before writing the desired value
to the output latch.
(3) Even if it is specified that data transfer from the buffer register to the output latch is to occur according to a
signal from the INTP0 pin, data transfer from the buffer register to the output latch occurs when the contents
of timer/counter 1 (TM1) coincide with the contents of the compare register (CR10).
To perform data transfer from the buffer register to the output latch only according to a signal from the INTP0
pin, perform one of the following points. Use of any of these methods does not allow use of the compare
register (CR10) for 8-bit timer/counter 1.
(a) Do not use 8-bit timer/counter 1.
(b) When using the capture/compare register (CR11) for 8-bit timer/counter 1 as the compare register, use the
compare register as an interval timer in a mode in which clearing occurs when the contents of the capture/
compare register (CR11) coincide with the contents of 8-bit timer 1 (TM1).
In this case, however, make sure that the contents of the compare register (CR10) are greater than those
in the CR11 register.
(c) When using the capture/compare register (CR11) for 8-bit timer/counter 1 as the capture register, use the
capture register only when it is guaranteed that the period of the valid edge of a signal input at INTP0 is
sufficiently shorter than the time required for the value in 8-bit timer 1 (TM1) to change from 0 to FEH.
In this case, set the compare register (CR10) to FFH, and clear timer/counter 1 after captured.
(d) If there is no problem, even if data transfer from the buffer register to the output latch is delayed by at least
one clock of 8-bit timer (TM1), and it is guaranteed that TM1 does not overflow, set the following:
• Specify that 8-bit timer/counter 1 is cleared after captured by the INTP0 signal.
• Specify that the INTP0 signal is not used as a trigger signal for data transfer through the real-time output
port.
• Specify that the compare register (CR10) is reset to 0H.
104
Timer interrupt
Set the interval
Set the value to be output next
in the P0L buffer register
Return
Advertisement
Table of Contents
