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µ PD78214 Sub-Series
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7.5 NOTES
7.5.1 Common Notes on All Timers/Counters
(1) When the registers listed below are rewritten while a counter is operating (with the CEm bit of register TMCn
is set), the counter can malfunction. The cause of such a malfunction is that when a hardware function change
made by the rewriting of a register conflicts with a state change of the function before the rewriting, which
change is to have priority is undefined.
Before rewriting these registers, be sure to stop counter operation for safety.
• Prescaler mode register (PRMn)
• Capture/compare control register (CRCn)
• Timer output control register (TOC)
• CMD2 bit of timer control register 1 (TMC1)
212
Fig. 7-130 Setting of Control Registers for Interval Timer Operation
(a) Timer control register 0 (TMC0)
7
6
5
×
0
0
TMC0
(b) Prescaler mode register 0 (PRM0)
7
6
5
PRS3
PRS2
PRS1 PRS0
PRM0
Fig. 7-131 Setting Procedure for Interval Timer Operation
Set count value in CR30 register
4
3
2
1
0
0
0
1
4
3
2
1
0
0
0
Interval timer
Set PRM0 register
CR30←n
Start counting
CE←1
INTC30 interrupt
0
0
Overflow flag
Enables counting TM0
0
0
Specifies count clock
(x/f
; where x = 16, 32, 64, 128, 256, or 512)
CLK
; Sets bit 7 of TMC0 to 1
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