Timing When External Wait Signal Is Used - NEC PD78212 User Manual

µ PD78214 Sub-Series
Note
f
CLK
A8-A15
(output)
AD0-AD7
ASTB (output)
RD (output)
WAIT (input)
Note
f
CLK
A8-A15
(output)
AD0-AD7
(output)
ASTB (output)
WR (output)
WAIT (input)
Note f : System clock frequency (f
CLK
366
Fig. 13-17 Timing When External Wait Signal Is Used
(a) Read timing
Lower
Hi-Z
address
(output)
(b) Write timing
Hi-Z
Lower
address
/2)
XX
Higher address
Data (input)
Higher address
Data
Hi-Z
Hi-Z