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Next, the processor clock control register (PCC) of the PD75402 is shown below. Setting of bit 1 of the PCC is
performed by a 4-bit memory handling instruction. At this time, ensure that bits 3, 2 and 0 are reset to "0" so that
the pattern "00
0" is written.
Fig. 5-17
Address
3
2
1
FB3H
PCC3 PCC2 PCC1
Note
1. Ensure that 0 is always written to PCC bit 0.
2. Unlike the PD75402A, in the PD75402, switching
s at 4.19 MHz) cannot be specified.
62
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
PD75402 Processor Clock Control Register Format
0
Symbol
0
PCC
CPU clock selection bits when f
0
Output = f
1
= f
When 4.19 MHz < f
0
Output = f
1
= f
f
: Main system clock oscillation circuit output frequency
XX
CPU operating mode control bit
0
0
0
1
1
0
1
1
4.19 MHz
XX
( ) : When f
= 4.19 MHz
XX
CPU Clock Frequency
/64 (65.5 kHz)
XX
/8 (524 kHz)
XX
5.0 MHz
XX
( ) : When f
= 4.91 MHz
XX
CPU Clock Frequency
/64 (76.7 kHz)
XX
/8 (614 kHz)
XX
Normal operating mode
HALT mode
STOP mode
Setting prohibited
is 2-step rather than 3-step. High-speed mode (0.95
1 Machine Cycle
15.3 s
19.1 s
1 Machine Cycle
13 s
1.63 s
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