NEC PD75402A User Manual page 115

Bus release detection flag (R)
RELD
4
Command detection flag (R)
CMDD
4
Acknowledge trigger bit (W)
When ACKT is set after the end of a transfer, ACK is output in synchronization with the next
SCK. After the ACK signal is output, ACKT is automatically cleared (0).
ACKT Note 1. ACKT must not be set (1) before completion of a serial tramsfer or during a
Acknowledge enable bit (R/W)
0
ACKE
1
Acknowledge detection flag (R)
ACKD
104
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
Clearing Conditions (RELD = 0)
When a transfer start instruction is
executed
When RESET is input
When CSIE = 0 (See Fig. 5-25)
When SVA and SIO do not match
when an address is received
Clearing Conditions (CMDD = 0)
When a transfer start instruction is
executed
When the bus release signal (REL) is
detected
When RESET is input
When CSIE = 0 (See Fig. 5-25)
transfer.
2. ACKT cannot be clearedby software.
3. When ACKT is set, ACKE should be reset to 0.
Disables automatic output of the acknowledge signal (outpt by ACKT is possibel).
When set before end of transfer
When set after end of transfer
Clearing Conditions (ACKD = 0)
When a transfer is started
When RESET is input
Setting Condition (RELD = 1)
When the bus release signal (REL) is de-
tected
Setting Condition (CMDD = 1)
When the command signal (CMD) is de-
tected
ACK is output is synchronization with the 9th
SCK clock cycle.
ACK is output in synchronization with SCK
immediately after execution of the setting
instruction.
Setting Condition (ACKD = 1)
When the acknowledge signal (ACK) is de-
tected (Synchronized with the rise of SCK)