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Note
Mnemonic
Operand
mem. bit
SET 1
f mem. bit
mem. bit
CLR 1
f mem. bit
mem. bit
SKT
f mem. bit
mem. bit
SKF
f mem. bit
SKTCLR
f mem. bit
AND 1
CY, f mem. bit
OR 1
CY, f mem. bit
XOR 1
CY, f mem. bit
addr
BR
$addr
BRCB
! caddr
CALLF
! faddr
RET
RETS
RETI
PUSH
rp
POP
rp
EI
IE
DI
IE
Note
Instruction Group
154
CHAPTER 9. INSTRUCTION SET
Machine
Bytes
Cycle
2
2
(mem. bit)
2
2
(f mem.bit)
2
2
(mem. bit)
2
2
(f mem. bit)
2
2 + S
Skip if (mem. bit) = 1
2
2 + S
Skip if (f mem. bit) = 1
2
2 + S
Skip if (mem. bit) = 0
2
2 + S
Skip if (f mem. bit) = 0
2
2 + S
Skip if (f mem. bit) = 1 and clear
2
2
CY
CY
2
2
CY
CY
2
2
CY
CY
–
–
PC
addr
10 – 0
(
The assembler selects the opti-
mum instruction from among
BRCB!, caddr, and BR$ addr.
1
2
PC
addr
10 – 0
2
2
PC
caddr
10 – 0
(SP–4) (SP –1) (SP–2)
2
2
(SP – 3)
0000
PC
faddr, SP
10 – 0
PC
(SP) (SP + 3) (SP + 2)
10 – 0
1
3
SP
SP + 4
PC
(SP) (SP + 3) (SP + 2)
10 – 0
1
3 + S
SP
SP + 4,
then skip unconditionally
PC
(SP) (SP + 3) (SP + 2)
10 – 0
1
3
PSW
(SP + 4) (SP + 5),
SP
SP + 6
1
1
(SP–1) (SP–2)
1
1
rp
(SP + 1) (SP) , SP
2
2
IME (IPS. 3)
2
2
IE
1
2
2
IME (IPS. 3)
2
2
IE
0
Addressing
Operation
Area
1
*2
1
*3
0
*2
0
*3
*2
*3
*2
*3
*3
(f mem. bit)
*3
(f mem. bit)
*3
(f mem. bit)
*3
*4
)
*5
*6
0, PC
10 – 0
*7
SP – 4
rp, SP
SP–2
SP + 2
1
0
Skip
Condition
(mem. bit) = 1
(f mem. bit) = 1
(mem. bit) = 0
(f mem. bit) = 0
(f mem. bit) = 1
None
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