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Fig. No.
5-32
Example of SBI Serial Bus System Configuration ........................................................................... 93
5-33
SBI Transfer Timing ............................................................................................................................. 95
5-34
Bus Release Signal ............................................................................................................................... 96
5-35
Command Signal .................................................................................................................................. 96
5-36
Address .................................................................................................................................................. 97
5-37
Slave Selection by Address ................................................................................................................ 97
5-38
Command .............................................................................................................................................. 98
5-39
Data ........................................................................................................................................................ 98
5-40
Acknowledge Signal ............................................................................................................................ 99
5-41
5-42
RELT, CMDT, RELD & CMDD Operation (Master) .......................................................................... 106
5-43
RELT, CMDT, RELD & CMDD Operation (Slave) ........................................................................... . 106
5-44
ACKT Operation .................................................................................................................................. 107
5-45
ACKE Operation .................................................................................................................................. 108
5-46
ACKD Operation ................................................................................................................................. 109
5-47
BSYE Operation .................................................................................................................................. 109
5-48
Pin Configuration Diagram ............................................................................................................... 112
5-49
Address Transmission from Master Device to Slave Device (WUP = 1) .................................... 114
5-50
Command Transmission from Master Device to Slave Device ................................................... 115
5-51
Data Transmission from Master Device to Slave Device .............................................................. 116
5-52
Data Transmission from Slave Device to Master Device .............................................................. 117
5-53
Example of Serial Bus Configuration .............................................................................................. 119
5-54
READ Command Transfer Format .................................................................................................... 121
5-55
WRITE & END Command Transfer Format ..................................................................................... 121
5-56
STOP Command Transfer Format .................................................................................................... 122
5-57
STATUS Command Transfer Format ............................................................................................... 123
5-58
STATUS Command Status Format .................................................................................................. 123
5-59
RESET Command Transfer Format .................................................................................................. 124
5-60
CHGMST Command Transfer Format ............................................................................................ . 124
5-61
Master and Slave Operations after an Error ................................................................................... 125
6-1
Interrupt Control Circuit Block Diagram .......................................................................................... 127
6-2
Interrupt Vector Table ........................................................................................................................ 128
6-3
Configuration of INT0 and INT2 ....................................................................................................... 130
6-4
INT0 Noise Elimination Circuit Input/Output Timing .................................................................... 131
6-5
INT2 Input Noise Elimination . ......................................................................................................... 131
6-6
Edge Detection Mode Register Format ........................................................................................... 132
6-7
IME Format .......................................................................................................................................... 132
6-8
Interrupt Servicing Procedure .......................................................................................................... 134
7-1
Standby Mode Reset Operation ....................................................................................................... 144
8-1
Reset Signal Acceptance ................................................................................................................... 146
8-2
Reset at Power-on .............................................................................................................................. 146
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