NEC PD75402A User Manual page 90

Fig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3)
Bus release trigger bit (W)
The bus release signal (REL) trigger output control bit. The SO latch is set (1) by setting this
RELT
bit (RELT = 1), after which the RELT bit is automatically cleared (0).
Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after
it is completed.
Command trigger bit (W)
The command signal (CMD) trigger output control bit. The SO latch is cleared (0) by setting
CMDT
this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).
Note SB0 must not be cleared during a serial transfer: Ensure that it is cleared before a transfer is started or after
it is completed.
Bus release detection flag (R)
When a transfer start instruction is
executed
RELD
When RESET is input
When CSIE = 0 (See Fig. 5-25)
When SVA and SIO do not match
4
when an address is received
Command detection flag (R)
When a transfer start instruction is
executed
CMDD
When tje bus release signal (REL) is
detected
When RESET is input
When CSIE = 0 (See Fig. 5-25)
4
Acknowledge trigger bit (W)
When ACKT is set after the end of a transfer, ACK is output in synchronization with the next
SCK. After th ACK signal is output, ACKT is automatically cleared (0).
ACKT
Note 1. ACKT must not be set (1) before completion of a serial tramsfer or during a
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
Clearing Conditions (RELD = 0)
Clearing Conditions (CMDD = 0)
transfer.
2. ACKT cannot be clearedby software.
3. When ACKT is set, ACKE should be reset to 0.
Setting Condition (RELD = 1)
When the bus release signal (REL) is de-
tected
Setting Condition (CMDD = 1)
When the command signal (CMD) is de-
tected
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