NEC PD75402A User Manual page 87

Fig. 5-25 Serial Operating Mode Register (CSIM) Format (2/2)
Wake-up function specification bit (W)
WUP
Note If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is output
after the BUSY release directive until the next fall of the serial clock (SCK). When setting WUP = 1, it is
necessary to confirm that the SB0 pin has been driven high after BUSY is released before setting WUP =
1.
Signal from address comparator (R)
COI*
When slave address register (SVA) and
shift register data do not match
* A COI read is valid only before the start or after completion of a serial transfer. During a transfer an indeterminate
value will be read. Also, COI data written by an 8-bit manipulation instruction is ignored.
Serial interface operation enable/disable specification bit (W)
CSIE
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CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
0 IRQCSI set at end of every serial transfer in each mode.
Used only in SBI mode. IRQCSI is set only when the address received after bus
1
release matches the slave address register data (wake-up status). SB0 is high
impedance.
Clearing Condition (COI = 0)
Shift Register Serial Clock
Operation Counter
Shift operation
0
disabled
Shift operation
1 Count operation
enabled
Setting Condition (COI = 1)
When slave address register (SVA) and shift
register data match.
IRQCSI Flag
Cleared Retained
Settable
SO/SB0 & SI Pins
Port 0 function only
Function in each
mode plus port 0
function