Chapter 8. Reset Function; Reset Signal Acceptance; Reset At Power-On - NEC PD75402A User Manual

When low level is input to the RESET pin, system reset is applied and the hardware enters the state shown in
Table 8-1.
When the RESET input goes from low level to high level, the reset state is released. Then, the contents of the
lower-order three bits of address 000H of the reset vector table are set into program counter (PC) bits 10 to 8 and
the contents of the low-order three bits of address 001H are set into PC bits 7 to 0 and the program branches and
begins executing from that branch address. Therefore, reset and starting from an arbitrary address is possible.
Initialize the contents of each register as required in the program.
The RESET pin is a Schmitt-triggered input with hysteresis characteristics at the threshold level. To prevent
misoperation by noise, a function which rejects narrow band noise by analog delay is also provided on the chip
(see Fig. 8-1).
For reset operation at power-on, provide an ample oscillation stabilization time from power-on to reset signal
acceptance as shown in Fig. 8-2.
RESET
V
DD
RESET
146

CHAPTER 8. RESET FUNCTION

CHAPTER 8. RESET FUNCTION
Fig. 8-1 Reset Signal Acceptance
Analog Analog
Delay Delay
Rejected Reset
as Noise Acceptance
Fig. 8-2 Reset at Power-on
Oscillation
Stabilization
Analog
Time
Delay
Reset
Release
Contents of reset
Analog
vector table set
Delay
in PC (PC initialize)
Reset
Release
Contents of reset
vector table set
in PC (PC initialize)
Reset branch destination
address instruction
execution
Reset branch
destination address
instruction execution