NEC PD75402A User Manual page 129

(10) Start of transfer
When the following two conditions are met a serial transfer is started by setting transfer data in the shift register
(SIO).
• The serial interface operatio enable/disable bit (CSIE) = 1.
• After an 8-bit serial transfer, the internal serial clock is stopped or SCK is high.
Note 1. The transfer will not be started if CSIE is set to "1" after data is written into the shift register.
2. Since the N-ch transistor must be turned off during data reception, FFH should be written to SIO
beforehand.
However, when the wake-up function specification bit (WUP) is 1, the N-ch transistor is always off, and
therefore FFH need not be written to SIO prior to reception.
3. If data is written to SIO when the slave is in the busy state, that data is not lost.
The transfer starts when the busy state is released and the SB0 input becomes high (ready state).
When an 8-bit transfer ends, the serial transfer stops automatically and the IRQCSI interrupt request flag is set.
Example In the following example the data in the RAM specified by the HL register is transferred to SIO, and at
the same time the SIO data is fetched into the accumulator and the serial transfer is started.
MOV XA, @HL ; Fetch send data from RAM
XCH XA, SIO ; Exchange send data with receive data and start transfer
(11) Points to note concerning SBI mode
(a) Detection of the slave selected/nonselected state is performed by detection of a match with a slave address
received after bus release (when RELD = 1).
An address match interrupt (IRQCSI) generated when WUP = 1 is normally used for this match detection.
Therefore, detection of selection/nonselection by the slave address should be performed with WUP = 1.
(b) For selection/nonselection detection without using an interrupt when WUP = 0, the address detection
method is not used: Instead, detection should be performed by transmission/reception of commands set
beforehand by the program.
(c) When WUP is set to 1 during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is
output following a BUSY release directive until the next fall of the serial clock (SCK). When WUP is set to
1, a check must be performed to ensure that SB0 has been driven high after BUSY is released before setting
WUP to 1.
118
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS