Digital Input/Output Port Operations - NEC PD75402A User Manual

5.1.4

Digital Input/Output Port Operations

Port and port pin operations when a data memory handling instruction is executed for a digital input/output port
differ according to the input/output mode setting (see Table 5-3). This is because, as can be seen from the input/
output port configurations, data fetched onto the internal bus is treated as pin data in input mode and as output
latch data in output mode.
(1) Operations when input mode is set
When a test instruction such as the SKT instruction, or an instruction which fetches port data as 4 bits onto the
internal bus (IN, MOV and bit operation instructions) is executed, individual pin data is manipulated.
When an instruction which performs a 4-bit transfer of accumulator contents to a port (OUT or MOV instruction)
is executed, the accumulator data is latched in the output latch. The output buffer remains off.
When an XCH instruction is executed, the individual pin data is input to the accumulator, and the accumulator
data is latched in the output latch. The output buffer remains off.
When an INCS instruction is executed, data comprising the individual pin data (4-bit) + 1 is latched in the output
latch. The output buffer remains off.
When a bit-wise data memory rewriting instruction such as the SET1/CLR1/SKTCLR instructions is executed, the
output latch for the specified bit can be rewritten as directed by the instruction, but the contents of the output latches
for the other bits are undefined.
(2) Operations when output mode is set
When a test instruction, bit input instruction, or an instruction which fetches port data as 4 bits onto the internal
bus is executed, the output latch contents are manipulated.
When an instruction which performs a 4-bit transfer of accumulator contents is executed, when the output latch
data is overwritten it is simultaneously output from the pins.
When an XCH instruction is executed, the output latch contents are transferred to the accumulator, and the
accumulator contents are latched in the output latches and output from the pins.
When an INCS instruction is executed, data comprising the output latch contents + 1 is latched in the output
latches and output from the pins.
When a bit output instruction is executed, the specified output latch bit is rewritten and output from the pin.
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
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