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Output
Signal Name
Device
Synchronization clock for
Serial Clock
Master
(SCK)
output of address/command/
data, ACK signal,
Synchronous BUSY signal,
etc.
Address/command/ data is
transferred in first 8 cycles.
Address
Master
8-bit data transferred in
synchronization with SCK
(A7 to A0)
after REL signl and CMD
signal output.
Master
8-bit data transferred in
synchronization with SCK
Command
after CMD signal only is
(C7 to C0)
output without output of REL
signal.
8-bit data transferred in
Data
Master/
synchronization with SCK
(D7 to D0)
slave
with no output of either REL
signal or CMD signal.
* 1. When WUP = 0, IRQCSI is always set on the 9th rise of SCK.
When WUP = 1, IRQCSI is set on the 9th rise of SCK only with an address is receive and that address matches the value of the slave address register
(SVA).
2. In data transmission/reception, when in the BUSY stare, the transfer starts after transition to the READY state.
Table 5-8 Signals in SBI Mode (2/2)
Definition
SCK
1
SB0
SCK
SB0
REL
SCK
SB0
SCK
SB0
Timing Chart
Exection of
instruction
to write to
2
7
8
9
10
SIO when
CSIE = 1
(serial
transfer
start
1
2
7
8
directive) *2
CMD
1
2
7
8
CMD
1
2
7
8
Output
Effect on
Meaning of
Condition
Signal
Flag
IRQCSI set
Timing of signal output
(rise of 9th
to serial data bus
SCK clock
cycle) *1
Address value of slave
device on serial bus
Directive, meddage,
etc., to slave device.
Data to ve processed by
slave or master device
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