Table of Contents
Advertisement
The format of the edge detection mode register (IM0) which is used to select the detected edge is shown in Fig.
6-6. IM0 is set by 4-bit memory handling instructions.
On an RESET input, all bits of IM0 are cleared to 0 and the rising edge is specified for INT0.
Address
3
FB4H
IM03
Note
As the interrupt request flag may be set when the edge detection mode register is modified, the following
procedure should be used: Disable interrupts and modify the mode register in advance, clear the interrupt
request flag with the CLR1 instruction, and then enable interrupts again. Also, when f
the sampling clock by modifying IM0, the interrupt request flag must be cleared after the elapse of 16
machine cycles following the mode register modification.
(3) Interrupt master enable flag (IME)
The interrupt master enable flag specifies acknowledgment enabled/disabled for all interrupts.
IME is manipulated by the EI/DI instructions.
With a RESET input, IME is cleared to 0 and acknowledgment of all interrupts is disabled.
Address
3
FB2H
IME
132
CHAPTER 6. INTERRUPT FUNCTIONS
Fig. 6-6 Edge Detection Mode Register Format
2
1
0
Symbol
0
IM01
IM00
IM0
Detected edge specification
0
0
0
1
1
0
1
1
Sampling clock specification
0
1
f
/64 (15.3 s: Operating at 4.19 MHz)
x
Fig. 6-7 IME Format
Interrupt master enable flag (IME)
All interrupts are disabled, vectored interrupts
0
are notinitiated.
Interrupt enabling/disabling is controlled by the
1
corresponding interrupt enable flag.
Rising edge specification
Falling edge specification
Rising and falling edge specification
Ignored (interrupt request flag is not set)
(0.95 s/1.91 s/15.3 s: operating at 4.19 MHz)
/64 is selected as
X
Advertisement
Table of Contents
