3
IM0
Sampling Clock
Noise Elimination
Circuit
INT
Edge
INT0/P10
Detection
Circuit
INTCSI
Rising Edge
INT2/P12
Detection
Circuit
Analog Delay Noise
Elimination Circuit
Fig. 6-1 Interrupt Control Circuit Block Diagram
Interrupt Enable Flag (IE
IRQBT
BT
IRQ0
IRQCSI
IRQ2
Internal Bus
IME
)
VRQ1
VRQ2
VRQ3
IST0
Decoder
Priority
Vector
Control
Table
Circuit
Address
Generation
Circuit
Standby Release Signal