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(b) Serial bus interface control register (SBIC)
When the 3-wire serial I/O mode is used, SBIC is set as shown below (see 5.5.3 (2) "Serial bus interface
control register" for full details of SBIC).
SBIC is manipulated by bit manipulation instructions.
Reset input clears the SBIC register to 00H.
The shaded area indicates bits used in the 3-wire serial I/O mode.
Address
7
6
FE2H
BSYE
ACKD
Should not used in 3-wire serial I/O mode
Remarks
(W)
Write only
Bus release trigger bit (W)
The command signal (REL) trigger output control bit. The SO latch is cleared (0) by setting
RELT
this bit (RELT = 1), after which the RELT bit is automatically cleared (0).
Command trigger bit
The command signal (CMD) Trigger output control bit. The SO latch is cleared (0) by setting
CMDT
this bit (CMDT = 1), after which the CMDT bit is automatically cleared (0).
Note
Bits other than RELT and CMDT should not be used in the 3-wire serial I/O mode.
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
5
4
3
ACKE
ACKT
CMDD
2
1
0
RELD
CMDT
RELT
Bus Release Trigger Bit (W)
Command Trigger Bit (w)
Symbol
SBIC
87
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