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Mnemonic
Note 1
Operand
mem. bit
SET 1
f mem. bit
mem. bit
CLR 1
f mem. bit
mem. bit
SKT
f mem. bit
mem. bit
SKF
f mem. bit
SKTCLR
f mem. bit
AND 1
CY, f mem. bit
OR 1
CY, f mem. bit
XOR 1
CY, f mem. bit
BR
$addr
BRCB
! caddr
CALLF
! faddr
RET
RETS
RETI
PUSH
rp
POP
rp
EI
IE
DI
IE
IN
A, PORTn
OUT
PORTn, A
HALT
STOP
NOP
Note
1. Instruction Group
2. Branch instructions
3. I/O instructions
4. CPU control instructions
158
CHAPTER 9. INSTRUCTION SET
B
1
0
B
B
1
0
1
0
0
1
1
0
B
B
1
0
1
0
0
1
1
0
B
B
1
0
1
0
1
1
1
0
B
B
1
0
1
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
(+16)
0
0
0
0
(+ 2)
(– 1)
1
1
1
1
(–15)
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
Operation Code
1
0
1
0
1
D
D
7
6
1
1
0
1
0
1
0
0
D
D
7
6
1
1
0
0
0
1
1
1
D
D
7
6
1
1
1
1
0
1
1
0
D
D
7
6
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
0
1
1
0
0
A
A
A
A
3
2
1
0
S
S
S
S
3
2
1
0
0
caddr
0
faddr
1
1
1
0
0
0
0
0
1
1
1
1
1
0
P
1
1
1
0
P
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
B
2
D
D
D
D
D
D
5
4
3
2
1
0
bit-addr
D
D
D
D
D
D
5
4
3
2
1
0
bit-addr
D
D
D
D
D
D
5
4
3
2
1
0
bit-addr
D
D
D
D
D
0
5
4
3
2
1
bit-addr
bit-addr
bit-addr
bit-addr
bit-addr
1
1
0
0
1
0
0
1
1
N
N
N
2
1
0
1
1
0
0
1
0
0
1
1
N
N
N
2
1
0
1
1
0
N
N
N
2
1
0
1
1
0
N
N
N
2
1
0
1
0
0
0
1
1
1
1
0
0
1
1
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