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Fig. 6-4 INT0 Noise Elimination Circuit Input/Output Timing
Sampling Cycle
(t
) or Less
SMP
INT0
Sheped
Output
1 to 2 Times t
SMP
(a)
INT0
Sheped
Output
(b)
INT0
Sheped
Output
2 or More Times
t
SMP
INT0
Sheped
Output
Remarks
t
= t
or 64/f
SMP
CY
Specification of the detected edge of the INT0 input and selection of the sampling clock is performed by the edge
detection mode register (IM0).
As signals are also input via the noise elimination circuit when the INT0 pin inputs data as a port, the input data
must be of sufficient width to avoid being eliminated as noise.
INT2 functions as an externally testable input which sets a testable flag on detection of a rising edge. Noise
elimination by the sampling clock is not performed, but as there is a function for eliminating pulses which are
narrower than the analog delay, a signal of adequate width must be input as in the case of INT0 (see Fig. 6-5).
INT2 Input
CHAPTER 6. INTERRUPT FUNCTIONS
t
SMP
L
Eliminated as Noise
H
L
Eliminated as Noise
H
XX
Fig. 6-5 INT2 Input Noise Elimination
Analog
Delay
Eliminated
as Noise
t
t
t
SMP
SMP
SMP
L
H
L
H
L
H
Analog
Delay
INT2 Input
Received
t
SMP
L
L
L
L
131
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