NEC PD75402A User Manual page 41

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP
Hardware Name (Symbol)
Address
b3
FE0H
Serial operation mode register (CSIM)
FE1H
CSIE
CMDD RELD
FE2H
SBI control register (SBIC)
FE3H
BSYE ACKD
FE4H
Serial I/O shift register (SIO)
FE6H
Slave address register (SVA)
FE8H
Port mode register Group A (PMGA)
FECH
Port mode register Group B (PMGB)
FF0H Port 0 (PORT 0)
FF1H Port 1 (PORT 1)
FF2H
Port 2 (PORT 2)
FF3H
Port 3 (PORT 3)
FF5H Port 5 (PORT 5)
FF6H Port 6 (PORT 6)
* 1. Bits 3 and 1: W; bit 2: R.
2. Bits 3 and 2: R; bits 1 and 0: W.
3. Bits 3 and 1: R/W; bit 2: R; bit 0: W.
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Table 3-4 PD75402A I/O Map (2/2)
b2 b1 b0
COI WUP 0
CMDT RELT
ACKE ACKT
No. of Manipulatable
Addressing
1 Bit 4 Bits 8 Bits
W
* 1
* 2
* 3
R/W
W
W
W
R R
R R
R/W R/W
R/W R/W
R/W R/W
R/W R/W
Bit
Manipula- Remarks
tion
0 must always be
mem. bit
written in bit 0.
Bit manipulation
mem. bit
only is possible
for all the bits.
11000 must
always be written
in the high-order
5 bits.
Bits 3 and 1 are
fixed to 0.
fmem. bit