5.1.6
Digital Input/Output Port Input/Output Timing
The timing for outputting data to the output latch and fetching pin data or output latch data onto the internal bus
is shown in Fig. 5-9.
(a) Data fetch by 1-machine-cycle instruction
(b) Data fetch by 2-machine-cycle instruction
Instruction
Execution
Input Timing
(c) Data latching by 1-machine-cycle instruction
(d) Data latching by 2-machine-cycle instruction
Instruction
Execution
Output Latch
(Output Pin)
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
Fig. 5-9 Digital Input/Output Port Input/Output Timing
1-Machine Cycles
Instruction
Manipulation
Execution
Instruction
Input Timing
2-Machine Cycles
Manipulation Instruction
Instruction
Manipulation Instruction
Execution
Output Latch
(Output Pin)
Manipulation Instruction
3
0
1
0
1
53