NEC PD75402A User Manual page 124

(7) Address match detection method
In the SBI mode, master address communication is used to select a specific slave and start communication.
Address match detection is performed by hardware. A slave address register (SVA) is provided, and IRQCSI is
set only when the address sent from the master and the value set is SVA match in the wake-up state (WUP = 1).
Note 1. Detection of the slave selected/nonselected state is performed by detection of a match with a slave
address received after bus release (when RELD = 1).
An address match interrupt (IRQCSI) generated when WUP = 1 is normally used for this match detection.
Therefore, detection of selection/nonselection by the slave address should be performed with WUP =
1.
2.
For selection/nonselection detection without using an interrupt when WUP = 0, the address detection
method is not used: Instead, detection should be performed by transmission/reception of commands
set beforehand by the program.
(8) Error detection
In the SBI mode, since the status of the serial bus SB0 pin during transmission is also written into the SIO shift
register of the transmitting device, transmission errors can be detected in the following ways:
(a) Comparison of pre-transmission and post-transmission SIO data
In this case, a transmission error is judged to have been generated if the two data items are different.
(b) Use of slave address register (SVA)
Transmission is performed after also setting the send data in the SVA register. After transmission the COI
bit of the serial operating mode register (CSIM) (the match signal from the address comparator) is tested: "1"
indicates normal transmission, and "0", a transmission error.
(9) Communication operation
With the SBI, the master normally selects the slave device to be communicated with from among the multiple
connected devices by outputting an address onto the serial bus.
After the target communication device has been determined, commands and data are exchanged between the
master device and slave device, thus implementing serial communication.
Data communication timing charts are shown in Figs. 5-49 through 5-52.
In the SBI mode, shift register shift operations are performed in synchronization with the fall of the serial clock
(SCK), and send data is latched in the SO latch and is output MSB-first from the SB0/P02 or P03 pin. Receive data
input to the SB0 pin is latched in the shift register on the rise of SCK.
CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS
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