Timing Constraints - Intel 80C188EC User Manual

INTERRUPT CONTROL UNIT
The AD15:13 pins are used for CAS2:0 information only during interrupt acknowledge cycles.
There is no need to latch the AD15:13/CAS2:0 signals during interrupt acknowledge cycles; the
8259A family devices have internal CAS latches that are activated by the INTA signal. The
8259A family devices ignore the state of the CAS lines except during interrupt acknowledge cy-
cles. The AD15:13/CAS2:0 lines begin driving the Slave ID as soon as it is available internally.
8.6.4.2

Timing Constraints

There are several timing constraints to be aware of when connecting an external 8259 device. The
following discussion is based on an analysis of the 82C59A-2 device specifications. The
82C59A-2 is the fastest 8259A family device currently available from Intel.
Minimum RD/INTA Pulse Width (T
the Chip-Select Unit or an external wait state generator). Minimum INTA pulse width can be met
for interrupt acknowledge cycles by inserting wait states as well.
Minimum Write Pulse Width (T
serting wait states into write cycles to the 82C59A-2.
Data Float After RD or INTA (T
11.76 MHz. Above 11.76 MHz, the 82C59A-2 device (or devices) must be buffered with a trans-
ceiver (a 74F245 or the equivalent). Without the transceiver, the 82C59-A2 device does not stop
driving the data bus in time for the next bus cycle, causing bus contention.
Back-to-Back Reads (T
required by the 82C59A-2 between two accesses of the same type. This recovery time specifica-
tion is violated above a processor frequency of 12.5 MHz. The simplest way to solve this problem
is to insert a "software wait state" in the programming code. The most common software wait
state is the "JMP $+2" instruction. "JMP $+2" ensures an uninterruptable delay of 14 clock cy-
cles. Figure 8-30 shows the use of the "JMP $+2" instruction in a typical programming sequence.
MOV DX, EXT59_ODD;ACCESS IMR (A0=1)
MOV AL, 07FH;UNMASK IR7 ONLY
OUT DX, AL
JMP $+2
MOV DX, EXT59_EVN
MOV AL, 0BH;READ ISR COMMAND
OUT DX, AL
Figure 8-30. Software Wait State for External 82C59A-2
8-46
) can be met for read cycles by inserting wait states (with
RLRH
) and Minimum Data Setup Time (T
WLWH
) can be guaranteed only below a processor frequency of
RHDZ
) and Back-to-Back Writes (T
RHRL
) can be met by in-
DVWH
) both refer to the recovery time
WHWL
;SOFTWARE WAIT STATE
;READ ISR (A0=1, ISR
;WILL BE SELECTED)