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INTERRUPT CONTROL UNIT
IR Line
Figure 8-28. Resetting the Edge Detection Circuit
8.6.3
Ready Generation
The on-chip 8259A modules do not supply a READY signal to the CPU during interrupt ac-
knowledge cycles. The hardware designer must ensure that a READY signal is applied to prop-
erly terminate interrupt acknowledge cycles. Wait states are not required for interrupt
acknowledge cycles that access the on-chip 8259A modules. External cascaded 8259A devices
may require wait states.
READY is automatically asserted for read and write accesses to the on-board 8259A modules
(through the Peripheral Control Block).
8.6.4
Connecting External 8259A Devices
There are several hardware concerns when cascading additional 8259 family devices to the on-
board master 8259A module. The master 8259A module has seven direct inputs that are available
for cascading. The interrupt capability of the 80C186/C188EC can be extended to 57 external in-
terrupts by connecting seven additional 8259 family devices to these seven pins (8 slave IRs × 7
master INT6:0 + INT7 = 57 total IRs). Polling may be used to extend I/O handling capability be-
yond 57 sources.
This section covers external cascading and applies to all of the 8259A family devices. Intel rec-
ommends the use of the 82C59A-2 device for cascading to the 80C186EC/C188EC family due
to its higher speed and lower power consumption compared with the older NMOS 8259A devic-
es.
A typical connection for an external cascaded 82C59A-2 device is shown in Figure 8-29. The
8259A device resides on the lower half of the 16-bit processor data bus in this example. The A0
address line is connected to latched A1 address line (8-bit systems would connect latched A0 to
the 8259A's A0 line). The 8259A device is hardwired for slave mode by strapping the SP/EN pin.
The CAS2:0 pins are connected to the AD15:13/CAS2:0 (for 8-bit systems, these are
A15:13/CAS2:0) lines from the processor.
8-44
T IRLH
A1237-0A
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