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10.2.4 Suspension of DMA Transfers Using the DMA Halt Bits
The DMA Module HALT Register (Figure 10-16) contains three bits that allow the system soft-
ware to suspend DMA transfers temporarily. The HNMI bit is set automatically whenever the
CPU receives an NMI . When the HNMI bit is set, no DMA transfers can occur from either mod-
ule. The HNMI bit is automatically cleared when an IRET instruction is executed. The HNMI bit
can be cleared by the system software if DMA transfers are desired during the NMI service rou-
tine.
Executing an INT2 instruction (NMI) does not set the HNMI bit.
The HDMA and HDMB bits are used to suspend transfers for module A and module B, respec-
tively. The HDMA and HDMB bits should be used instead of HNMI when suspending transfers
under normal circumstances. This ensures that the system software will not inadvertently inter-
fere with an NMI service routine.
The mask bits (HMI, HMA, HMB) allow the modification of individual halt bits without per-
forming a read-modify-write operation on the DMA Halt Register.
10.2.5 Initializing the DMA Unit
Use the following sequence when programming the DMA Unit:
1.
Program the source and destination pointers for all used channels.
2.
Program the inter-module priority.
3.
Program the DMA Control Registers in order of highest-priority channel to lowest-
priority channel.
DIRECT MEMORY ACCESS UNIT
10-27
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