Special Mask Mode, Poll Mode And Register Reading: Ocw3 - Intel 80C188EC User Manual

INTERRUPT CONTROL UNIT
8.4.4.3

Special Mask Mode, Poll Mode and Register Reading: OCW3

OCW3 (Figure 8-19) is used to control Special Mask Mode, Poll Mode, and register reading.
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
ESMM Enable
Special
Mask Mode
SMM Special
Mask Mode
POLL Poll
Command
ERR Enable
Register
Read
RSEL Read
Register
Select
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
8-34
Operation Command Word 3
OCW3 (accessed through MPICP0, SPICP0)
Controls Special Mask Mode and register reading.
Reset
Bit Name
State
X
X
X
X
X
Figure 8-19. OCW3 Register
E S
S M
0 M M 0
M
Function
ESMM must be set to modify SMM.
Set SMM to select Special Mask Mode (allows
lower-priority interrupts to interrupt higher-
priority handlers).
Setting this bit starts the polling sequence.
Polling always takes precedence over reading
the 8259A registers.
ERR must be set to modify RSEL.
RSEL chooses which register is read during the
next read cycle. When RSEL is set, the In-
Service Register is read; when RSEL is
cleared, the Interrupt Request Register is read.
0
P E R
O R S
1 L R E
L L
A1227-0A