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SERIAL COMMUNICATIONS UNIT
11.2.3 Programming in Mode 0
Programming is much easier in Mode 0 than in the asynchronous modes. Configuring SxCON
(Figure 11-13 on page 11-15) for Mode 0 requires only two steps:
1.
Program M2:0 with the correct combination for Mode 0.
2.
If the Clear-to-Send feature is desired, set the CEN bit.
The serial port is now configured for Mode 0. To transmit, write a character to SxTBUF. The TI
and TXE bits reflect the status of SxTBUF and the transmit shift register. Note that the SBRK bit
is independent of serial port mode functions in Mode 0.
Receptions in Mode 0 are controlled by software. To begin a reception, set the REN bit in Sx-
CON. The RI bit must be zero or the reception will not begin. Data begins shifting in on RXD as
soon as REN is set. The asynchronous error flags (OE, FE and PE) and break flags (DBRK0 and
DBRK1) are invalid in Mode 0.
11.3 HARDWARE CONSIDERATIONS FOR THE SERIAL PORT
There are several interface considerations when using the serial port.
11.3.1 CTS Pin Timings
When the Clear-to-Send feature is enabled, transmissions will not begin until the CTS pin is as-
serted while a transmission is pending. Figure 11-15 shows the recognition of a valid CTS.
The CTS pin is sampled by the rising edge of CLKOUT. The CLKOUT high time synchronizes
the CTS signal. On the falling edge of CLKOUT, the synchronized CTS signal is presented to the
serial port. CTS is an asynchronous signal. The setup and hold times are given only to ensure rec-
ognition at a specific clock edge. When CTS is asynchronously, it should be asserted for at least
1½ clock cycles to guarantee that the signal is recognized.
CTS is not latched internally. If CTS is asserted before a transmission starts, the subsequent trans-
mission will not begin. A write to SxTBUF "arms" the CTS sense circuitry.
11.3.2 BCLK Pin Timings
The BCLK pin can be configured as the input to the baud timebase clock. The baud timebase
clock increments the BxCNT register. However, the BCLK signal does not run directly into the
baud timebase clock. BCLK is first synchronized to the CPU clock (Figure 11-16.) The internal
synchronization logic uses a low-to-high level transition on BCLK to generate the baud timebase
clock that increments the BxCNT register. The CPU recognizes a low-to-high transition by sam-
pling the BCLK pin low, then high.
11-18
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