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BCLK
PICCLK
Lag = T21B (FRC Mode BCLK to PICCLK offset)
Figure 7-9. FRC Mode BCLK to PICCLK Timing
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INIT#)
T
=
T9 (GTL+ Input Hold Time)
t
T
=
T8 (GTL+ Input Setup Time)
u
T
=
T10 (RESET# Pulse Width)
v
T
=
T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
w
T
=
T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
x
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
T
= T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
y
T
= T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
z
Figure 7-10. System Bus Reset and Configuration Timings
0.7 V
Lag
0.7 V
T
y
Safe
ELECTRICAL SPECIFICATIONS
T
u
T
t
T
v
T
z
Valid
T
w
Valid
000919
T
x
000 6
000764a
7-27
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