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CS1
CS2
Figure 3-16. Generating a Normally Ready Bus Signal
The READY input has two major timing concerns that can affect whether a normally ready or
normally not-ready signal may be required. Two latches capture the state of the READY input
(see Figure 3-14 on page 3-15). The first latch captures READY on the phase 2 clock edge. The
second latch captures READY and the result of first latch on the phase 1 clock edge. The follow-
ing items define the requirements of the READY input to meet ready or not-ready bus conditions.
•
The bus is ready if both of these two conditions are true:
— READY is active prior to the phase 2 clock edge, and
— READY remains active after the phase 1 clock edge.
•
The bus is not-ready if either of these two conditions is true:
— READY is inactive prior to the phase 2 clock edge, or
— READY is inactive prior to the phase 1 clock edge.
A normally not-ready system must generate a valid READY input at phase 2 of T2 to prevent
wait states. If it cannot, then running without wait states requires a normally ready system. Figure
3-17 illustrates the timing necessary to prevent wait states in a normally not-ready system. Figure
3-17 also shows how to terminate a bus cycle with wait states in a normally not-ready system.
Wait State Module
Enable
ALE
Load
CLKOUT
Clock
BUS INTERFACE UNIT
Out
READY
A1081-0A
3-17
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