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CONTENTS
Figure
11-18
Master/Slave Example .............................................................................................11-25
12-1
Block Diagram of the Watchdog Timer Unit ...............................................................12-2
12-2
Watchdog Timer Reset Circuit....................................................................................12-2
12-3
Generating Interrupts with the Watchdog Timer.........................................................12-3
12-4
WDTOUT Waveforms.................................................................................................12-6
12-5
WDT Reload Value (High) ..........................................................................................12-9
12-6
WDT Reload Value (Low).........................................................................................12-10
12-7
WDT Count Value (High)..........................................................................................12-11
12-8
WDT Count Value (Low)...........................................................................................12-12
13-1
Simplified Logic Diagram of a Bidirectional Port Pin ..................................................13-2
13-2
Simplified Logic Diagram of an Output Port Pin .........................................................13-4
13-3
Simplified Logic Diagram of an Open-Drain Bidirectional Port ...................................13-5
13-4
Port Control Register (PxCON) ..................................................................................13-8
13-5
Port Direction Register (PxDIR)..................................................................................13-9
13-6
Port Data Latch Register (PxLTCH) .........................................................................13-10
13-7
Port Pin State Register (PxPIN) ...............................................................................13-11
14-1
80C187-Supported Data Types..................................................................................14-8
14-2
80C186 Modular Core Family/80C187 System Configuration....................................14-9
14-3
80C187 Configuration with a Partially Buffered Bus.................................................14-12
14-4
80C187 Exception Trapping via Processor Interrupt Pin..........................................14-14
15-1
Entering/Leaving ONCE Mode ...................................................................................15-1
A-1
Formal Definition of ENTER ........................................................................................ A-3
A-2
Variable Access in Nested Procedures ....................................................................... A-4
A-3
Stack Frame for Main at Level 1.................................................................................. A-4
A-4
Stack Frame for Procedure A at Level 2 ..................................................................... A-5
A-5
Stack Frame for Procedure B at Level 3 Called from A............................................... A-6
A-6
Stack Frame for Procedure C at Level 3 Called from B .............................................. A-7
B-1
Input Synchronization Circuit....................................................................................... B-1
xvi
FIGURES
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