Vcc_Core; Power Sequencing; Vccp Output Requirements; Power On Sequencing Timing Diagram - Intel Pentium M Processor Design Manual

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Intel Pentium M Processor and Intel
Platform Power Delivery Guidelines
11.3.3 V
CC_CORE
There is only one enable pin, VR_ON, used to enable the outputs of the voltage regulator. When
VR_ON is low, all output voltage rails (V
0 V state. When VR_ON is high, V
Figure 128.

Power On Sequencing Timing Diagram

† Desired, but not required feature of a processor voltage regulator compliant controller. When not
implemented by the voltage regulator controller, both the CLK_ENABLE# and the t
implemented by platform control logic.
Figure 128
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Pentium
timing requirements between VR_ON, output supply stabilization, and all power good signals.
11.3.4 V
CCP
The V
CCP
the Intel Pentium M processor, the Intel
port when it is used. For the ICH3-S, this rail is known as V
194
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E7501 Chipset Platform

Power Sequencing

VR_PWRGD
depicts a number of signals that may or may not be platform visible or used in an Intel
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M processor/Intel E7501 chipset design. For more details on the relationships and
Output Requirements
output voltage rail provides power to the Intel Pentium M processor system bus rail for
and V
CC_CORE CCP
and V are ramp up at the same time.
CCP CC_CORE
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E7501 MCH, the Intel ICH3-S, and ITP700FLEX debug
CPU_IO.
) are driven to a
timer must be
CPU-PWRGD
The processor voltage
Design Guide
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