Reloading The Watchdog Timer Down Counter - Intel 80C188EC User Manual

WATCHDOG TIMER UNIT
Figure 12-3(b) shows the circuit necessary to generate an NMI from WDTOUT. NMI is edge sen-
sitive and level latched. The inverter is needed to prevent an NMI immediately upon reset.
When using interrupts to recover from a system upset, pay close attention to "Using the Watch-
dog Timer as a General-Purpose Timer" on page 12-6.
(a) (b)
Processor Processor
WDTOUT WDTOUT
INT x
NMI
A1304-0A
Figure 12-3. Generating Interrupts with the Watchdog Timer
When the Watchdog Timer Unit is used as a system watchdog, the goal of the system software is
to prevent the 32-bit down counter from ever reaching zero. This is accomplished by periodically
reloading the down counter with the Watchdog Timer Reload Value.

12.2.1 Reloading the Watchdog Timer Down Counter

A special LOCKed byte write instruction sequence to the Watchdog Timer Clear (WDTCLR)
Register reloads the down counter. The WDTCLR Register expects a sequence of two bytes,
which must be written within the same LOCKed instruction. The first byte must be 0AAH and
the second must be 55H. Writing any other data values or using two separate LOCKed instruc-
tions will not reload the down counter. Examples 12-1 and 12-2 show the code necessary to re-
load the down counter when the Peripheral Control Block is located in I/O and memory space,
respectively.
In embedded control systems, the Watchdog Timer is typically reloaded at the end of the control
loop. For systems that do not execute a single looped program, the Watchdog Timer is usually
reloaded during the system timer "tick" service.
12-3