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UCS
AD7:0
LA15:1
RD
AD15:8
3.5.2
Write Bus Cycles
Figure 3-21 illustrates a typical write bus cycle. The bus cycle starts with the transition of ALE
high and the generation of valid status bits S2:0. The bus cycle ends when WR transitions high
(inactive), although data remains valid for one additional clock. Table 3-4 lists the two types of
write bus cycles.
Note: A and BHE are not used.
0
Figure 3-20. Read-Only Device Interface
BUS INTERFACE UNIT
CE
O 0-7
27C256
A 0-14
OE
OE
A 0-14
27C256
O 0-7
CE
A1105-0A
3-23
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