Intel 80C188EC User Manual page 97

BUS INTERFACE UNIT
Signals From CPU
A19:16
S2:0
AD15:8
AD7:0
ALE
Figure 3-11. Demultiplexing Address Information
S2
0
0
0
0
1
1
1
1
3-12
4
I
3
I
STB
OE
8
I
STB
OE
8
I
STB
OE
Table 3-1. Bus Cycle Types
Status Bit
S1 S0
0 0 Interrupt Acknowledge
0 1 I/O Read
1 0 I/O Write
1 1 Halt
0 0 Instruction Prefetch
0 1 Memory Read
1 0 Memory Write
1 1 Idle (passive)
Latched
Address Signals
4
LA19:16
O
3
LS2:0
O
8
LA15:8
O
8
O LA7:0
Operation
A1102-0A