Intel 80C188EC User Manual page 154

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At the second falling CLKOUT edge after the internal clocks resynchronize, the processor deas-

serts RESOUT. Bus activity starts seven CLKOUT periods after recognition of RESIN in the log-

ic high state. If an alternate bus master asserts HOLD during reset, the processor immediately

asserts HLDA and will not prefetch instructions.

CLOCK GENERATION AND POWER MANAGEMENT

Figure 5-7. Warm Reset Waveform

Minimum RESIN

low time 4 CLKOUT