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Register Name:
Register Mnemonic:
Register Function:
15
P
S
E
N
Bit
Bit Name
Mnemonic
PSEN
Power Save
Enable
F2:0
Clock
Division
Factor
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
CLOCK GENERATION AND POWER MANAGEMENT
Power Save Register
PWRSAV
Enables and sets clock division factor.
Reset
State
0H
Setting this bit enables Power Save mode and
divides the internal operating clock by the value
defined by F2:0. Clearing this bit disables
Power-Save mode and forces the CPU to
operate at full speed. PSEN is automatically
cleared whenever an interrupt occurs.
0H
These bits control the clock division factor used
when Power Save mode is enabled. The
allowable values are listed below:
F2 F1 F0 Divisor
0 0 0 By 1 (undivided)
0 0 1 By 4
0 1 0 By 8
0 1 1 By 16
1 0 0 By 32
1 0 1 By 64
1 1 0 Reserved
1 1 1 Reserved
Figure 5-14. Power-Save Register
0
F
F
F
2
1
0
A1123-0A
Function
5-21
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