Table of Contents
Advertisement
TIMER/COUNTER UNIT
Register Name:
Register Mnemonic:
Register Function:
15
E
I
I
N
N
N
H
T
Bit
Bit Name
Mnemonic
RTG
Retrigger
P
Prescaler
EXT
External
Clock
ALT
Alternate
Compare
Register
CONT
Continuous
Mode
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)
9-8
Timer 0 and 1 Control Registers
T0CON, T1CON
Defines Timer 0 and 1 operation.
R
I
U
Reset
State
X
This bit specifies the action caused by a low-to-high
transition on the TMR INx input. Set RTG to reset the
count; clear RTG to enable counting. This bit is
ignored with external clocking (EXT=1).
X
Set to increment the timer when Timer 2 reaches its
maximum count. Clear to increment the timer at ¼
CLKOUT. This bit is ignored with external clocking
(EXT=1).
X
Set to use external clock; clear to use internal clock.
The RTG and P bits are ignored with external clocking
(EXT set).
X
This bit controls whether the timer runs in single or
dual maximum count mode (see Figure 9-4 on page
9-6). Set to specify dual maximum count mode; clear
to specify single maximum count mode.
X
Set to cause the timer to run continuously. Clear to
disable the counter (clear the EN bit) after each
counting sequence.
M
R
P
E
A
C
T
X
L
G
T
T
Function
0
C
O
N
T
A1297-0A
Advertisement
Table of Contents
